—L Œΐ‰οŽΠ@Τ—tƒƒWƒbƒN
                                       RedLeafLogic

‰οŽΠˆΔ“ΰ
LSI έŒvƒT[ƒrƒX
FPGA ‘Ξ‰žƒT[ƒrƒX
‘g‚ݍž‚έƒVƒXƒeƒ€Ώ•‰

‚ζ‚€‚±‚»i—LjΤ—tƒƒWƒbƒN‚Μƒz[ƒ€ƒy[ƒW‚Φ





‹Zpƒƒ‚
              ›  LSIέŒv
              ›  FPGA
              ›  ‘g ‚ݍž‚έ
              ›  ŒŸ Ψ




@V’…ξ•ρ
 
 2010  3/31         LGPL uart16550 ”­•\
      http://opencores.org/project,systemverilog-uart16550
    
 2008 8/25    ‹Zpƒƒ‚
@@@@@@ ›ŒŸΨ  E VMM‚Ζ‚Ν’Η‰Α
                           E cvc_counterΰ–Ύ’Η‰Α
 2008 8/21    ƒz[ƒ€ƒy[ƒWŠJέB
1

—LŒΐ‰οŽΠΤ—tƒƒWƒbƒN@                       @@Copyright(c) 2008 RedLeafLogic, Ltd. all rights reserved